TTL circuits are derived from a common logic structure of which FIG. 1 shows a conventional arrangement. In this NAND gate connected between terminals for receiving low and high supply voltages V.sub.EE and V.sub.CC, input signals represented here by voltages V.sub.I1 and V.sub.I2 are provided to the corresponding emitters of a multiple-emitter NPN input transistor Q1. Its base is coupled through a resistor R1 to the V.sub.CC supply. Elements Q1 and R1 form an input circuit for the gate.
The collector of transistor Q1 is connected to the base of an NPN phase-splitting transistor Q2 in an output circuit of the gate. The Q2 collector is coupled through a resistor R2 to the V.sub.CC supply. The Q2 collector is further connected to the base of an NPN transistor Q3. Its emitter drives an NPN output transistor Q4 and is coupled through a resistor R3 to the Q4 emitter. The interconnected collectors of the Darlington pair Q3 and Q4 are coupled through a resistor R4 to the V.sub.CC supply.
The Q2 emitter drives the base of an NPN output transistor Q5 whose emitter is tied to the V.sub.EE supply. A pull-down resistor R5 is connected between the Q5 base and the V.sub.EE supply. An output voltage signal V.sub.O is provided from interconnection of the Q5 collector and the Q4 emitter.
To understand the operation of this gate, assume that at least one of inputs V.sub.I1 and V.sub.I2 --e.g., input V.sub.I1 --is initially at a low voltage or logical "0" (hereafter just "0") below the input switching point. Transistors Q2 and Q5 are off because current through resistor R1 to the V.sub.I1 input terminal pulls the Q2 base voltage to a low value. Transistors Q3 and Q4 are on. Output V.sub.O is at a high voltage or logical "1" (hereafter just "1").
Let voltage V.sub.I1 be raised to a "1" above the input switching point. The R1 current decreases and starts flowing through the Q1 base-collector junction to transistor Q2. It turns on and draws current through resistor R2 to turn off transistors Q3 and Q4. Part of the R2 current goes to transistor Q5 which turns on and actively pulls voltage V.sub.O down to a "0". The reverse occurs when input V.sub.I1 is returned to "0". The R1 current increases and begins flowing to the V.sub.I1 terminal. Transistors Q2 and Q5 turn off while transistors Q3 and Q4 turn on to actively pull voltage V.sub.O up to "1".
As phase splitter Q2 turns off, charge carriers in its base discharge through input transistor Q1 to the V.sub.I1 terminal. This enables the gate to have a relatively high switching speed. However, the maximum input current (when input V.sub.I1 is low) is typically on the order of milliamperes. This level is too high for many applications.